This invention relates to a 16B/20B encoder, and particularly to a parallel implementation of 8B/10B encoders for use in Fibre Channel Arbitrated Loop designs (FCAL).
Recently, the computer industry has adopted use of a fibre channel to handle data transmission between devices. Fibre channels represent significant advantages over Small Computer Standard Interface designs (SCSI). Fibre channels provide significantly higher bandwidths, up to 100 Megabytes per second, compared to 2 to 20 Megabytes per second for SCSI designs. Fibre channels provide greater connectivity of up to 126 devices including the host, as opposed to 15 devices in a typical SCSI environment. The fibre channel can be attached with a single connector and does not require a switch. A fibre channel using fibre optics operates at distances of up to 30 meters between devices, and up to 10 kilometer for an entire channel as compared to a total length of up to 25 meters for SCSI environments. In SCSI environments, errors in data transmission are detected through use of parity, whereas in fibre channels errors are identified by a running disparity and Cyclic Redundancy Check (CRC).
The FCAL is an industry standardized system employing a byte-oriented DC balanced (0,4) run length limited rate 8B/10B partitioned block transmission code scheme. The FCAL operates at a clock frequency of 106.25 MHz. One form of an 8B/10B encoder/decoder is described in U.S. Pat. No. 4,486,739 granted Dec. 4, 1984 for "Byte Oriented DC Balanced (0,4) 8B/10B Partitioned Block Transmission Code" by Franaszek et al., which is incorporated herein by reference. The Franaszek 8B/10B encoder/decoder partitions an 8-bit input word into a 5-bit portion and a 3-bit portion. The 5-bit portion is encoded to a 6-bit output, and the 3-bit portion is encoded with a control bit to a 4-bit output.
A binary, or two-level, code employs ones and zeros usually assigned respective positive and negative values. Run length is defined as the number of identical contiguous symbols (ones or zeros) that appear in a data stream. A large number of contiguous binary ones will produce a highly positive DC signal, whereas a large number of contiguous binary zeros will produce a highly negative DC signal. However, it is important to maintain DC balance in the signal, both in long data strings as well as short data strings. Thus, on a (0,4) code, a symbol is followed by no more than four contiguous identical symbols (meaning a data stream may contain a string of up to five identical symbols before one of opposite value). (The "0" in the 0,4 notation means that a symbol may be followed by no less than zero contiguous identical symbols--meaning that any given symbol may be followed by a symbol of same or opposite value.) The (0,4) code disclosed in the Franaszek et al. patent permits only four characters that might generate five identical contiguous symbols, three of those characters being special characters. Hence, except for those four characters, the (0,4) code disclosed in the Franaszek et al. patent is effectively a (0,3) code.
The disparity of a block of data is the difference between the numbers of ones and zeros in the block. To adjust the DC level of the output string, the Franaszek et al. apparatus compares the running disparity from prior words to the disparity of the current word portion encoded. The output word portion, or a complement thereof, is then output. For example, if the running disparity is +1 and the current output word portion has a disparity of +2, the output portion is complemented to a word portion with a disparity of -2 and a -1 disparity is passed to the next encoding stage. The maximum disparity possible in the Franaszek et al. scheme is +3 and -3, and the disparity at the bounds between the 6-bit output and 4-bit output portions is either +1 or -1. Since the Franaszek et al. encoder is designed so a zero disparity is not possible, the disparity at the bounds between the 6-bit and 4-bit portions is at the minimum values of .+-.1.
In the Franaszek et al. scheme, the running disparity is passed from one encoding stage to the next, so that the running disparity from the 5B/6B encoder stage is held to encode the 3-bit input portion for the same word in the 3B/4B stage, and the running disparity from the 3B/4B encoder stage is held to encode the 5-bit input portion of the next word in the 5B/6B encoder stage. The holding of the running disparity between the stages required the two encoder stages be operated during different portions of the clock cycle. The output registers therefore are operated on separate portions of the clock.
To achieve wider data paths, a parallel version of the Franaszek 8B/10B encoder was implemented in VHSIC Hardware Description Language (VHDL) format. In the parallel version, one of the 8B/10B encoders encoded the upper half of the 16-bit input word while the other 8B/10B encoder encoded the lower half of the 16-bit word. The disparity was passed in sequence so that the running disparity of the upper 6-bit word portion was passed to the upper 3B/4B encoder, the running disparity of the upper 4-bit word portion was passed to the lower 5B/6B encoder, the running disparity of the lower 6-bit word portion was passed to the lower 3B/4B encoder, and the running disparity of the lower 4-bit word portion was passed to the upper 5B/6B encoder for the next word. To avoid holding each of the running disparities one-half cycle as in the original Franaszek et al. design, the parallel design operated the encoders and buffers on the same clock cycle and held the running disparity of the lower 6-bit word portion for later encoding in the upper 3B/4B encoder. The disparity of the upper 6-bit word portion was combinationally passed to the lower 3B/4B encoder, the disparity of the upper 4-bit word portion was combinationally passed to the lower 5B/6B encoder, and the disparity of the lower 4-bit word portion was combinationally passed to the upper 5B/6B encoder. Considering of a second of the 8B/10B encoders. The running disparity of the 4-bit output sub-block associated with the second 8B/10B encoder is held for processing by the 5B/6B encoder of the first 8B/10B encoder. Hence, during a single clock cycle, the running disparity of the second 4-bit output sub-block of a previous word is combined with the disparity of the current first 6-bit output sub-block and the running disparity of both current 6-bit output sub-blocks and the current first 4-bit output sub-block are combined with the disparities of both current 4-bit output sub-blocks and the current second 6-bit output sub-block, thereby selectively complementing all output sub-blocks for a current data block during a single clock cycle.
According to one aspect of the present invention, a forced disparity control responds to a special character bit and a forced disparity bit to force the running disparity of the 5B/6B encoder of the first encoder to a selected polarity. Preferably, the forced disparity control also passes the running disparity of the selected polarity of the immediately prior 4-bit output sub-block of the second 8B/10B encoder to the 5B/6B encoder of the first 8B/10B encoder.
According to another aspect of the present invention, an end-of-frame control responds to the running disparity of the immediately prior 4-bit output sub-block of the second 8B/10B encoder and an end-of-frame bit to selectively complement a bit of the current 3-bit input sub-block.
In another form of the present invention, a 16-bit data block is partitioned into an upper 5-bit sub-block, an upper 3-bit sub-block, a lower 5-bit sub-block and a lower 3-bit sub-block. During a single clock cycle, a first 5B/6B encoder portion encodes the upper 5-bit sub-block to produce an upper 6-bit sub-block, a first 3B/4B encoder portion encodes the upper 3-bit sub-block to produce an upper 4-bit sub-block, a second 5B/6B encoder portion encodes the lower 5-bit sub-block to produce a lower 6-bit sub-block, and a second 3B/4B encoder portion encodes the lower 3-bit sub-block to produce a lower 4-bit sub-block. During the same clock cycle, the running disparities of the upper 6-bit sub-block, the upper 4-bit sub-block and the lower 6-bit sub-block are simultaneously combinationally passed to the first 3B/4B encoder portion, the second 5B/6B encoder portion and the second 3B/4B encoder portion, respectively. During the next clock cycle, the running disparity of the lower 4-bit sub-block is passed to the first 5B/6B encoder.
More particularly, a binary data encoding apparatus according to the present invention produces a DC balanced run length limited rate 16B/20B code from an unconstrained input data stream that includes consecutive 16-bit data blocks. A first 8B/10B encoder receives an upper 8 bits of a data block and a second 8B/10B encoder receives a lower 8 bits of the data block. The first 8B/10B encoder includes a 5B/6B encoder for encoding an upper 5-bit sub-block into a 6-bit output data sub-block, and a 3B/4B encoder for encoding an upper 3-bit sub-block into a 4-bit output data sub-block. The first 8B/10B encoder also includes means for determining a disparity of the current 6-bit and 4-bit output sub-blocks and for determining a running disparity associated with each. The 3B/4B encoder of the first 8B/10B encoder is responsive to the disparity of the current upper 4-bit sub-block and to the running disparity of the current upper 6-bit sub-block to selectively complement the current upper 4-bit sub-block to reduce running disparity. The second 8B/10B encoder includes a 5B/6B encoder for encoding a lower 5-bit sub-block into a 6-bit output data sub-block, and a 3B/4B encoder for encoding a lower 3-bit sub-block into a 4-bit output data sub-block. The second 8B/10B encoder also includes means for determining a disparity of the current 6-bit and 4-bit output sub-blocks and for determining a running disparity associated with each. The 5B/6B encoder of the second 8B/10B encoder is responsive to the disparity of the current lower 6-bit sub-block and to the running disparity of the current upper 4-bit sub-block to selectively complement the current lower 6-bit sub-block to reduce running a 16-bit input data word composed of two 8-bit portions; the 16B/20B encoder provided the upper 8-bit portion during a first clock cycle and the lower 8-bit portion during the next clock cycle.
However the 16B/20B encoder required buffering both before and after the encoder to permit the 3-bit and 5-bit codes to be staged in and the 4-bit and 6-bit codes to be staged out and alignment of the full 20-bit output word. As in the prior Franaszek et al. design, the additional buffering represented increased gate count for the fibre channel port. Moreover, the parallel version required at least two clock cycles to encode a 16-bit input word to a 20-bit output word, thereby affecting system timing.